Notebook
What I'm currently up to
My research lab notebooks, one per project. Every design decision and measurement gets an entry on the day it happens, with the method and the scripts and data to reproduce it. Claims I haven't measured yet are tagged to verify.
Project
SRAM compute-in-memory macro
A digital SRAM compute-in-memory macro in the ASAP7 7 nm PDK, laid out and verified with my own OpenLayout EDA flow.
- 11 decisions
- 1 measurement
- 1 open
- 2 tooling
Now
- – Route b2SRAMsbc_INT8x8 (D10, D11): BL/BLB down the columns, Pk[7:0] to the bottom edge, WL / X per row; then DRC, LVS, connectivity.
- – Decide the reduction and accumulator: one fused carry-save tree (8 P bits per column plus the registered sum / carry fed back, one carry-propagate add at the end) vs. popcount, cross-column add and a ripple accumulator. Signed INT8: MSB complement plus a preloaded constant (weights); invert P and add 1 on the input's MSB cycle.
- – Bit-exact Python reference model of the 8-weight dot product before the adder schematics.
Project
ML-based SoC floorplanning
A learning-based floorplanner for a small RP2350-class SoC, with polygonal blocks and ASAP7-informed power density; the CIM macro supplies measured block data.
No entries yet
Open notebook →Latest entries
- T2Oct 16, 2026Tooling notes from assembling the arrayToolingSRAM CIM
- D11Oct 16, 2026DRIVE2b: one dual-inverter drive cell per rowRowSRAM CIM
- D10Oct 16, 2026Array assembly: on the fin grid, bus pinsArraySRAM CIM
- D9Oct 16, 2026b2SRAMsbc NOR pMOS: 2 finsBitcellSRAM CIM
- D8Oct 16, 2026Back to the 2-bit cell: a 4-row array of 8 INT8 weightsArchitectureSRAM CIM
- T1Oct 14, 2026OpenLayout/xschem fixes found while designingToolingSRAM CIM