ML-based SoC floorplanning
A learning-based floorplanner for a small RP2350-class SoC, with polygonal blocks and ASAP7-informed power density; the CIM macro supplies measured block data.
How this notebook works
Every design decision and every measurement gets one entry, written when it happens and appended in date order. Each day starts a new heading, and every entry names the topic it touches (see Entries by topic at the end). The fields of an entry: Question, Options, Method, Result, Decision, Revisit if. Claims that are reasoning but not yet measured are marked to verifylike this. Scripts live in scripts/, raw data in data/, next to this file (~/papers/notebook/ml-soc on the VM).
Project.A learning-based floorplanner for a small SoC: a reference block set modeled after an RP2350-class microcontroller die (CPU cores, GPU, PCIe, USB PHY, SRAM, flash control, ADC, programmable I/O, analog and clock circuitry), with blocks as arbitrary polygons rather than rectangles and per-block power density informed by ASAP7. A PyTorch model proposes placements, written to an intermediate format and rendered by a custom viewer. Measured block data from the SRAM compute-in-memory macro (the sram-cim notebook) feeds the block generator.
Rendered from ml-soc/notebook.tex on GitHub; synced Oct 21, 2026, 11:52 PM CDT.